Non-volatile memory devices are constructed such that previously stored data is not erased, even when no power is supplied o the device. Non-volatile Semiconductor Memories (NVSM) may be classified into a floating gate group and a stacked gate group. The NVSMs of the stacked gate group have two or more dielectric films stacked in double or triple. The stacked gate structure is widely employed in cell transistors of the non-volatile memory device.
A typical stacked gate structure includes a tunnel oxide film, a floating gate, a dielectric film, and a control gate electrode stacked on a channel region of the cell transistor in succession. A cell transistor having a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure has been suggested as a means for increasing a surface area of the floating gate in a high density non-volatile memory device package.
As expected, an SONOS non-volatile memory device has read, program, and erase operations. In the program operation, data programming is performed by applying a program voltage to a gate and a drain of a transistor of the cell to form hot electrons which tunnel a gate insulating film. These hot electrons are captured by a nitride film adjacent to the drain. On the other hand, in the erase operation, data is erased by removing the voltage from the gate, the drain, and the source and applying an erase voltage to the semiconductor substrate to drive the electrons captured by the nitride film into the semiconductor substrate.
Referring to FIG. 1, a prior art non-volatile memory device having an SONOS structure has a cell region located in an active region of a P type semiconductor substrate 10. In FIG. 1, the active region is defined in a field region of the semiconductor device 10 by a device isolation film 13 filling a trench 11. A gate oxide film 15 is formed on the entire surface of the cell region of the semiconductor substrate 10. Gate electrodes 21, 23 are formed on the gate oxide film 15. The gate electrodes 21, 23 are spaced a distance from each other. A third gate electrode 35 is located between the first gate electrode 21 and the second gate electrode 23. The third gate electrode 35 is formed after depositing a nitride film 31 and an oxide film 33 on the gate oxide film 15.
The gate oxide film 15, the nitride film 31, and the oxide film 33 of the third gate electrode 35 together form an ONO (Oxide-Nitride-Oxide) film 30. The gate oxide film 15 serves as the lower tunneling oxide film of the ONO film 30. The nitride film 31 deposited on the gate oxide film 15 serves as the trap nitride film of the ONO film 30. The oxide film 33, which is in direct contact with the third gate electrode 35, serves as the upper oxide film of the ONO film 30.
The above described prior art non-volatile memory device having the SONOS structure is fabricated by: forming a gate insulating film 15 on the cell region of the semiconductor substrate 10; stacking a polysilicon layer on the gate oxide film 15; and removing unnecessary portions of the polysilicon layer by photo-etching to form the first and second electrodes 21, 23. Then, the third gate electrode 35 is formed by successively stacking the nitride film 31 and the oxide film 33 on the gate insulating film 15 and the first and second gate electrodes 21, 23, stacking a polysilicon layer on the oxide film 33, and then selectively removing portions of the polysilicon layer, the oxide film 33, and the nitride film 31 by photo-etching.
In prior art devices, the nitride film 31 for storing data is in contact with the third gate electrode 35 through the oxide film 33 and has the same area as the third gate electrode 35. As a result, the area for storing data is limited. Consequently, improving the degree of device concentration has not been easy.